It is a sponsored article dropped at you by Siemens.
Format versus schematic (LVS) comparability is an important step in built-in circuit (IC) design verification, making certain that the bodily structure of the circuit matches its schematic illustration. The first purpose of LVS is to confirm the correctness and performance of the design. Historically, LVS comparability is carried out throughout signoff verification, the place devoted instruments examine structure and schematic knowledge to establish any inconsistencies or errors. Nonetheless, uncovering errors on the signoff stage results in time-consuming iterations that delay design closure and time to market. Whereas early-stage LVS comparability may mitigate these points, it typically generates tens of millions of error outcomes as a result of incomplete standing of the design.
To deal with these challenges, we developed a shift-left methodology, permitting designers to carry out LVS comparability earlier within the design movement. By incorporating LVS checks at earlier phases, design groups can catch errors sooner and cut back the variety of iterations required throughout signoff. Let’s take a deeper take a look at how a shift-left LVS verification method can improve designer productiveness and speed up verification.
The Calibre nmLVS™ Recon Examine answer introduces an clever shift-left course of for quick and exact LVS comparability earlier within the design cycle. It automates the black boxing of incomplete blocks and facilitates computerized port mapping, permitting designers to realize quicker LVS iterations on early-stage designs.
Challenges of conventional LVS verification
Within the conventional LVS verification course of, designers should confirm the structure towards its schematic illustration to make sure that the ultimate product features as meant. As a result of all design blocks have to be accomplished and prepared for closing comparability, verification groups wait till signoff phases to carry out thorough checks. Any errors found throughout this late-stage LVS run can set off extra verification iterations, resulting in wasted time and sources. Designers are then caught in a cycle of re-running the LVS course of every time a repair or replace is carried out, leading to a bottleneck throughout signoff.
Designers may run LVS examine earlier, though within the early phases of design many blocks are usually not but finalized, making a complete LVS comparability impractical. Working LVS on incomplete designs can generate tens of millions of error messages, a lot of which aren’t actionable as a result of they originate from the uncompleted parts of the structure. This overwhelming variety of outcomes makes it troublesome to pinpoint precise design points, rendering conventional LVS strategies impractical for early-stage verification.
As proven in determine 1, the verification movement may be extra complicated when design blocks are accomplished at totally different instances, driving a number of iterations of verification checks as every block is built-in into the general structure.
Fig. 1: Design verification cycle with blocks at totally different ranges of completion.
Shifting left for early LVS verification
Implementing a shift-left methodology for LVS verification means performing structure vs. schematic comparisons earlier within the design cycle, earlier than all blocks are finalized. To allow this, the movement should assist flexibility in coping with incomplete designs and permit for extra focused verification of important blocks and connections.
One solution to obtain that is by way of automation strategies like black boxing and port mapping. By abstracting the inner particulars of incomplete blocks whereas preserving their exterior connectivity data, the verification movement may be tailor-made to concentrate on interactions between accomplished and incomplete sections of the design. Automated port mapping, however, ensures that every one exterior connections between structure and schematic are accurately aligned for correct early-stage comparisons.
A brand new method to early LVS verification
A sophisticated methodology for early-stage LVS verification leverages these automated processes to speed up the shift-left verification course of. As an example, clever black boxing of incomplete blocks can considerably cut back the variety of error outcomes generated, making it simpler for verification groups to establish precise connectivity points between blocks.
The shift-left movement additionally advantages from the usage of a strong comparability engine that may analyze structure and schematic knowledge shortly and effectively, skipping pointless operations and calculations. This method focuses on the toughest issues early within the movement, leading to fewer errors found on the signoff stage and in the end dashing up design closure.
The flows illustrated in determine 2 exhibits how this shift-left methodology streamlines the verification course of by decreasing pointless steps and specializing in important design points.
Fig. 2: The normal full LVS movement with all steps (left) vs. the Calibre nmLVS Recon movement (proper).
Benefits of early LVS examine
Adopting a shift-left methodology for LVS verification gives a number of key advantages to semiconductor design groups:
Early detection of errors: By performing LVS comparisons earlier within the design movement, errors may be recognized and resolved earlier than they change into deeply embedded within the design. This proactive method reduces the chance of pricey rework and minimizes the variety of iterations wanted throughout signoff.
Accelerated design verification: Automating the comparability course of streamlines design verification, permitting designers to establish and resolve points effectively, even when all blocks are usually not finalized. This results in quicker total circuit verification and reduces the effort and time required for guide inspection.
Improved collaboration and debugging: With a centralized platform for verifying design correctness and sharing suggestions, early-stage LVS verification promotes collaboration throughout design groups. Engineers can isolate points extra successfully and supply insights to their colleagues, enhancing total design high quality.
Elevated design confidence: Guaranteeing alignment between structure and schematic representations from the early phases of design boosts confidence within the closing product’s correctness. By the point the design reaches signoff, many of the important connectivity points have already been resolved.
Actual-world functions
Calibre nmLVS Recon has demonstrated important advantages in actual design initiatives, together with 10x runtime enhancements and 3x decrease reminiscence necessities. A verification group at Marvell, for instance, enhanced their LVS movement over the complete design cycle utilizing Calibre nmLVS SI, attaining quicker verification instances and improved effectivity.
Conclusion
Shifting LVS examine duties earlier into the design movement gives important advantages to IC design groups. Our novel method to early top-level LVS comparability automates black boxing and port mapping so designers can carry out complete verification even when all blocks are usually not finalized. This accelerates design verification, improves collaboration, and enhances design confidence in semiconductor design workflows.
Study extra by downloading my latest technical paper “Speed up design verification with Calibre nmLVS Recon Examine.”
